cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 1/9 MTEA2N15L3 cystek product specification n-channel enhancement mode power mosfet MTEA2N15L3 bv dss 150v i d 3a r dson @v gs =10v, i d =1.6a 125m (typ) r dson @v gs =5.5v, i d =1a 141m (typ) description the MTEA2N15L3 is a n-channel enhancement-mode mosfet, providing the designer with the best combination of fast switching, ruggedized device de sign, low on-resistance and cost effectiveness. the sot-223 package is universally preferred for a ll commercial-industrial surface mount applications. features ? single drive requirement ? fast switching characteristic ? repetitive avalanche rated ? pb-free lead plating and halogen-free package symbol outline MTEA2N15L3 sot-223 ordering information device package shipping MTEA2N15L3-0-t3-g sot-223 (pb-free lead plating and halogen-free package) 2500 pcs / tape & reel g d s d g gate d drain ssource environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t3 : 2500 pc s / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 2/9 MTEA2N15L3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 150 gate-source voltage v gs 20 v continuous drain current @v gs =10v, t c =25 c 5.2 continuous drain current @v gs =10v,t c =100c 3.3 continuous drain current @v gs =10v,t a =25 c 3 continuous drain current @v gs =10v,t a =70 c i d 2.4 pulsed drain current i dm 16 *1 a t c =25 8.3 t c =100 3.3 t a =25 2.8 total power dissipation t a =100 p d 1.1 w operating junction and storage temp erature range tj, tstg -55~+150 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 15 c/w thermal resistance, junction-to-ambient, max r th,j-a 45 *3 c/w note : 1. pulse width limited by maximum junction temperature 2. duty cycle 1% 3. surface mounted on 1 in2 copper pad of fr-4 board, 120 c/w when mounted on minimum copper pad characteristics (t c =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 150 - - v v gs =0, i d =250 a v gs(th) 2.0 3.3 4.0 v v ds = v gs , i d =250 a g fs *1 - 4.5 - s v ds =10v, i d =1.6a i gss - - 100 na v gs = 20 - - 1 v ds =120v, v gs =0 i dss - - 25 a v ds =120v, v gs =0, tj=125 c - 125 160 m v gs =10v, i d =1.6a r ds(on) *1 - 141 180 m v gs =5.5v, i d =1a dynamic ciss - 536 - coss - 57 - crss - 21 - pf v gs =0v, v ds =25v, f=1mhz
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 3/9 MTEA2N15L3 cystek product specification characteristics (t c =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions qg *1, 2 - 12 - qgs *1, 2 - 2.2 - qgd *1, 2 - 4.9 - nc v ds =75v, v gs =10v, i d =3a t d(on) *1, 2 - 6 - tr *1, 2 - 12 - t d(off) *1, 2 - 17 - t f *1, 2 - 4 - ns v ds =25v, i d =1a, v gs =10v, r gs =6 source-drain diode i s *1 - - 2.1 i sm *3 - - 8.4 a v sd *1 - 0.76 1.3 v i f =i s , v gs =0v trr - 40 - ns qrr - 100 - nc i f =i s , di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. recommended soldering footprint
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 4/9 MTEA2N15L3 cystek product specification typical characteristics typical output characteristics 0 2 4 6 8 10 12 14 16 0246810 v ds , drain-source voltage(v) i d , drain current(a) 10v, 9v,8v,7v,6v v gs =5v v gs =4v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 1.6 -60 -20 20 60 100 140 180 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 100 1000 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 100 200 300 400 500 600 700 800 900 1000 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.8 1.2 1.6 2 2.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =3a r ds( on) @ tj=25c : 127 m v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =3a
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 5/9 MTEA2N15L3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 -60 -20 20 60 100 140 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) v ds =10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 02468101214 total gate charge---qg(nc) v gs , gate-source voltage(v) v ds =75v i d =3a maximum safe operating area 0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 10 s 100 s r ds( on) limit t a =25c, tj(max)=150c, v gs =10v, r ja =45c/w single pulse maximum drain current vs junction temperature 0 0.5 1 1.5 2 2.5 3 3.5 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =10v, r ja =45c/w
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 6/9 MTEA2N15L3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 2 4 6 8 10 12 14 16 0246810 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 50 100 150 200 250 300 1e-05 0.0001 0.001 0.01 0.1 1 10 100 pulse width(s) peak transient power (w) t j(max) =150c t a =25c ja =45c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =45 c/w
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 7/9 MTEA2N15L3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 8/9 MTEA2N15L3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c880l3 issued date : 2012.10.03 revised date : 2013.10.25 page no. : 9/9 MTEA2N15L3 cystek product specification sot-223 dimension *: typical inches 321 f b a c d e g h a1 a2 i style: pin 1.gate 2.drain 3.source marking: 3-lead sot-223 plastic surface mounted package cystek package code: l3 device name date code ea2n15 millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1142 0.1220 2.90 3.10 g 0.0551 0.0709 1.40 1.80 b 0.2638 0.2874 6.70 7.30 h 0.0098 0.0138 0.25 0.35 c 0.1299 0.1457 3.30 3.70 i 0.0008 0.0039 0.02 0.10 d 0.0236 0.0315 0.60 0.80 a1 *13 o - *13 o - e *0.0906 - *2.30 - a2 0 o 10 o 0 o 10 o f 0.2480 0.2638 6.30 6.70 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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